`timescale 1ns / 1ps
module top_32bit;
    reg [31:0] A,B;
    reg [2:0] F;
    wire [31:0]R;

    initial begin
        A = 32'd23;
        B = 32'd12;
        F = 3'b000;
        # 2 F= 3'b001;
        # 2 F= 3'b010;
        # 2 F = 3'b011;
        # 2 F= 3'b101;
        # 2 F= 3'b100;
        
        # 5 A = 32'h235b;
        B = 32'h3423;
        F = 3'b000;
        # 2 F= 3'b001;
        # 2 F= 3'b010;
        # 2 F = 3'b011;
        # 2 F= 3'b101;  
        # 1 $finish;
    end

    ALU2 alu(.R(R),.A(A),.B(B),.F(F));
   initial
  begin
    $dumpfile("test.vcd");
    $dumpvars(0, alu);
  end
endmodule
module ALU2(R,A,B,F);
    input [31:0] A,B;
    input [2:0]F;
    output reg [31:0]R;
    always @(*)begin
        case(F)
            3'b000:R=A+B;
            3'b001:R=A+1;
            3'b010:R=A-B;
            3'b011:R=A-1;
            3'b101:R=A*B;
            3'b100:R=A*B;
            default:R=32'b0;
        endcase
    end
endmodule
